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Guild: wafer.space Community
Channel: 📐 - Designing / 🕰️-analog / IO ESD
After: 2026-07-31 11:59 p.m.
Before: 2026-09-01 12:00 a.m.
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[2026-08-05 2:23 p.m.] 246tnt



[2026-08-05 2:23 p.m.] 246tnt
Ok, there are some small diodes on the input path after the resistor. But still, the main clamp are the actual drive transistors AFAICT.


[2026-08-05 2:36 p.m.] brunny95
The small diodes are standard (from what I've seen). Usually the path is: ESD main protections (GT mos or similar) - resistor - "small diodes" - core of the circuit


[2026-08-05 2:37 p.m.] chips4makers
If properly designed output drivers can indeed also be used as ESD protection. This is using the so-called snap-back behavior. I believe [this](https://siliconvlsi.com/explain-the-snapback-phenomenon-in-nmos-devices/) should explain something. I used 0.18um TSMC when @imec and both IO NMOS and PMOS were designed to have that capability.

{Embed}
https://siliconvlsi.com/explain-the-snapback-phenomenon-in-nmos-devices/
Explain the snapback phenomenon in NMOS devices - Siliconvlsi
The snapback phenomenon in NMOS devices is an important aspect in understanding their behavior and reliability.
2026-08_media/Snapback-mechanism-in-NMOS-1-5DD4E.png


[2026-08-05 2:40 p.m.] chips4makers
It is known to me as secondary protection and the purpose is to get some extra voltage drop over the resistance during an ESD event to protect the connected gates.
The diode also has a capacitance so the R-C acts as a low-pass filter on the input though so high frequency stuff typically needs IO with custom ESD protection.


[2026-08-05 2:42 p.m.] 246tnt
Tx both, yeah I knew the secondary protection thing. But never heard of snapback.


[2026-08-05 9:51 p.m.] mole99
Here are the ESD guidelines from the PDK: https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_14_4.html
It seems like the snapback behavior is indeed used for ESD protection.


[2026-08-07 6:22 p.m.] namibj
There are ESD implants available specifically only for thick oxide area's sd-diffusion.


[2026-08-07 6:27 p.m.] namibj
There's also a trick were you employ something like a gate-triggered TRIAC that's constructed to bascially experience a safe and depending on details maybe or maybe-not power-cycle-requiring latchup to clamp the ESD voltage below what a passive diodes-to-PDN-rails arrangement could do, to be useful whenever thin-oxide devices are used to interact with pads.

An example that comes to mind would be e.g. DDR3 which is nominally 1.5V and fairly intense on the IO power draw due to combination of frequency, receive-side-termination, and ofc sheer wire count.


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